| 摘要 |
A unified memory and a controller thereof are provided to emulate pseudo-NOR operation and an ATA format non-volatile NAND flash memory by receiving an address/data in a random address formant, and mapping the data/address to one of an NOR memory, a RAM, or a ROM operated as a cache for the NAND flash memory. The first bus receives an address and data signal from a host device(20). The second bus interfaces with the RAM(16) and the third bus interfaces with the NAND flash memory(14). The ROM stores a boot code for initializing operation of the memory controller. An MCU(Micro Control Unit)(12) receives the first address from the fist bus, maps the first address to the second address of the NAND flash memory, and operates the RAM as the cache for the data to or from the second address of the NAND flash memory. The MCU maintains data consistency between the data stored in the second address of the NAND flash memory and the data stored in the RAM functioning as the cache.
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