发明名称 Systems and methods for the emulation of TDM circuits over a real-time scheduled packet network
摘要 A system and method to emulate any TDM circuit on a Real-Time Scheduled Packet Network. The TDM circuit can be any serial or parallel bit stream, of any bit rate, and can either be synchronized to the Real-Time Scheduled Packet Network, or can be asynchronous to the network. The present system and method determines the requisite descriptors of a scheduled IP itinerary for any emulated TDM circuit.
申请公布号 US7239638(B2) 申请公布日期 2007.07.03
申请号 US20030383698 申请日期 2003.03.07
申请人 AVAYA TECHNOLOGY, LLC 发明人 WISLER DALE J.;REITH HOWARD C.;MILLEY DAVID A.
分类号 H04L12/56;H04L12/28 主分类号 H04L12/56
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