Single transistor memory cell with reduced programming voltages

摘要

A transistor fabrication method includes forming an electrode overlying a channel of a semiconductor on insulator (SOI) substrate. Source/drain structures are formed in the substrate on either side of the channel. The source/drain structures include a layer of a second semiconductor over a first semiconductor. The first and second semiconductors have different bandgaps. The second semiconductor extends under the gate electrode. The source/drain structures may be formed by doping the source/drain regions and etching the doped regions selectively to form voids. A film of the second semiconductor is then grown epitaxially to fill the void. A film of the first semiconductor may be grown to line the void before growing the second semiconductor. Alternatively, the second semiconductor is a continuous layer that extends through the channel body. A capping layer of the first semiconductor may lie over the second semiconductor in this embodiment.