| 摘要 |
A method for fabricating a flash memory device is provided to increase a coupling ratio by expanding an overlapped area between a floating gate and a control gate. A tunnel oxide layer(21) and a nitride layer are formed on a substrate(20), and then are partially etched to form a trench on the nitride layer. A first polycrystalline silicon layer(24) is formed on a bottom portion, and a sidewall of an oxide layer is formed on a sidewall of the trench. A second polycrystalline silicon layer(26) is formed on the first polycrystalline silicon layer to form a floating gate(27). The sidewall of the oxide layer is removed, and a gate dielectric layer(28) is formed on the floating gate to form a third polycrystalline silicon layer on the entire surface. An etching process for planarization is preformed on the third polycrystalline silicon layer to form a control gate(29).
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