SEMICONDUCTOR MEMORY DEVICE

摘要

A semiconductor memory device is provided to output plural test pattern data to an external test apparatus only when all memory blocks normally operate, by generating an output control signal controlling output of test pattern data according to the operation of the memory blocks. A memory cell array comprises a plurality of memory regions. An address decoding part generates signals selecting all of the memory regions simultaneously by decoding an address applied from the outside during a read operation in a test. A data input/output control part(30) receives test pattern data applied from the outside during a writing operation in the test and then writes the test pattern data to each of the memory regions, and reads the test pattern data outputted from one memory region during a reading operation in the test. A data input/output part(5) transmits the test pattern data to the data input/output control part during the writing operation, and outputs the data outputted from the data input/output control part to the outside in response to an output control signal during the reading operation. A test control signal generation part(40) generates the output control signal determining whether to output data by comparing the test pattern data outputted from each memory region during the reading operation.