LATCH CIRCUIT AND FLIP-FLOP CIRCUIT WITH SINGLE EVENT IMMUNITY

摘要

PROBLEM TO BE SOLVED: To provide a latch circuit and a flip-flop circuit preventing a single event phenomenon from being generated and eliminating the effect of a single event transient (SET) phenomenon on the circuits even in the case of the single event transient phenomenon. SOLUTION: The latch circuit is constituted of a dual port inverter and a dual port clocked inverter not including a transmission gate in order to narrow a strong electric field region to be formed. The effect of the SET phenomenon is eliminated by providing a delay time to a clock, in order to prevent a hold time from being increased due to the delay time, a leading edge delay clock is given to one storage node so as to delay transition from the storage node and the whole latch mode to a through node. COPYRIGHT: (C)2007,JPO&INPIT