发明名称 System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values
摘要 A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be processed at full processor efficiency without cycles wasted due to branch latency. Data to be processed are divided into two groups based on whether or not they satisfy a given condition by e.g., steering each to one of the two index vectors. Once the data have been segregated in this way, subsequent processing can be performed without conditional operations, processor cycles wasted due to branch latency, incorrect speculation or execution of unnecessary instructions due to predication. Other examples of conditional operations include combining one or more input vectors into a single output vector based on a condition vector, conditional vector switching, conditional vector combining, and conditional vector load balancing.
申请公布号 US2007150700(A1) 申请公布日期 2007.06.28
申请号 US20060511157 申请日期 2006.08.28
申请人 发明人 DALLY WILLIAM J.;RIXNER SCOTT;OWENS JOHN D.;KAPASI UJVAL J.
分类号 G06F15/00;G06F9/30;G06F9/315;G06F9/32;G06F9/38 主分类号 G06F15/00
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