Driver device of plasma display panel

摘要

To improve the power recovery rate of a driver device of a PDP. An output buffer circuit 10 is constituted by a totem-pole circuit where two NchMOS transistors Q 1 and Q 2 are cascade-connected, and the connection point (VOUT) of the two MOS transistors are connected to a data electrode C 0 of a display cell. A level shift circuit 11 is constituted by a CMOS circuit and drives the output buffer circuit 10 . An electric charge recovery circuit 13 is connected to a power supply VDD 2 of the output buffer circuit 10 , and it recovers and reuses electric charges remaining on the data electrode C 0 after the discharge of the display cells. A power supply control circuit 12 controls so that the power supply voltage of the level shift circuit 11 is higher than the sum of the power supply voltage of the output buffer circuit 10 and the threshold voltage of the MOS transistors for a period of time during a recovery/reuse cycle of the electric charge recovery circuit 13.