| 摘要 |
Disclosed is a method of manufacturing a phase-change memory in which the lower electrode of the phase-change memory device is formed using barrier metal for forming a metal interconnection and a via in damascene and dual damascene processes. The method includes the steps of patterning an insulating layer on a semiconductor substrate, sequentially forming barrier metal and metal on the patterned insulating layer, polishing the metal by a CMP process to planarize the metal and patterning the planarized barrier metal to a lower electrode of a desired phase-change memory device, depositing an insulating layer on the patterned lower electrode, forming a hole in the deposited insulating layer, and forming an upper electrode on the resultant material to pattern the upper electrode, and depositing an insulating layer on the upper electrode and forming a via for connecting a metal interconnection and the lower electrode to each other. Therefore, additional deposition for forming the lower electrode is not necessary. Also, copper (Cu) and copper alloy are used, interconnection resistance is reduced to be stabilized so that it is possible to improve the characteristic of the semiconductor device.
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