发明名称 |
MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTERGRATED CIRCUIT MEMORY DEVICE |
摘要 |
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. |
申请公布号 |
EP1800311(A1) |
申请公布日期 |
2007.06.27 |
申请号 |
EP20050799571 |
申请日期 |
2005.09.12 |
申请人 |
RAMBUS, INC. |
发明人 |
WARE, FREDERICK, A.;LAI, LAWRENCE;BELLOWS, CHAD, A.;RICHARDSON, WAYNE S. |
分类号 |
G11C8/12;G11C8/16 |
主分类号 |
G11C8/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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