发明名称 METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE
摘要 A method for forming a metal wiring in a semiconductor device is provided to improve reliability of the metal wiring by preventing the generation of a bridge between metal wirings. An interlayer dielectric(21) having a low pattern density region(200) and a high pattern density region(210) is formed on a structure(20). The interlayer dielectric is etched to form a via hole exposing a portion of the substrate. A metal film is formed on the interlayer dielectric to bury the via hole. The metal film is subjected to primary chemical mechanical polishing until the interlayer dielectric of low pattern density region is exposed. The metal film is subjected to secondary chemical mechanical polishing until the interlayer dielectric of high pattern density region is exposed. Then, the interlayer dielectric is subjected to third chemical mechanical polishing until the interlayer dielectric of high pattern density region is exposed.
申请公布号 KR20070066304(A) 申请公布日期 2007.06.27
申请号 KR20050127324 申请日期 2005.12.21
申请人 MAGNACHIP SEMICONDUCTOR, LTD. 发明人 PARK, KI YEOP
分类号 H01L21/28 主分类号 H01L21/28
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