发明名称 |
Fast buffer pointer across clock domains |
摘要 |
Retiming circuitry for retiming a data signal transmitted from a first environment under control of a first clock signal to a second environment under control of a second clock signal, said first and second clock signals having a known repeat relationship, the retiming circuitry comprising a plurality of delay elements for delaying said data signal; a plurality of inputs connected to said delay elements for receiving said data signal at respectfully different delays; selection means for selecting the data signal at one of said inputs based on said known repeat relationship; and an output for outputting said selected data signal.
|
申请公布号 |
US2007139085(A1) |
申请公布日期 |
2007.06.21 |
申请号 |
US20060545079 |
申请日期 |
2006.10.06 |
申请人 |
STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED |
发明人 |
ELLIOT PAUL;BENNETT PETER |
分类号 |
H03K5/01 |
主分类号 |
H03K5/01 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|