发明名称 Method of fabricating reduced subthreshold leakage current submicron NFET's with high III/V ratio material
摘要 A method of fabricating an enhancement mode semiconductor device comprises providing a compound semiconductor substrate, epitaxially growing on the substrate a first portion of a buffer, the first portion including gallium arsenide (GaAs), growing a second portion of the buffer, the second portion including a high V/III ratio and high aluminum (Al) mole fraction aluminum gallium arsenide (AlGaAs), and epitaxially growing a stack of compound semiconductor layers on the buffer. An enhancement mode semiconductor device is then formed in the stack.
申请公布号 US2007138507(A1) 申请公布日期 2007.06.21
申请号 US20050303776 申请日期 2005.12.16
申请人 GLASS ELIZABETH C;HARTIN OLIN L;HENRY HALDANE S;JAMET PHILIPPE O;ZHANG LISA Z;PELCZYNSKI MICHAEL W 发明人 GLASS ELIZABETH C.;HARTIN OLIN L.;HENRY HALDANE S.;JAMET PHILIPPE O.;ZHANG LISA Z.;PELCZYNSKI MICHAEL W.
分类号 H01L29/739 主分类号 H01L29/739
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