A data masking circuit is provided to receive DM data even at a high frequency operation, by enabling DM data by an external clock signal(PLCKWC) and disabling DM data enabled by a reset signal. In a data masking circuit of a semiconductor memory device, a first latch part(200) latches data input in response to a first signal. A logic gate(300) performs an AND operation of the first signal and the output of the first latch part. A second latch part(400) latches the output of the logic gate and determines to disable the output of the logic gate by a second signal. A signal generation circuit(100) generates the first signal and the second signal synchronized with an external clock.
