| 摘要 |
This is a system which provides a train of output pulses that duplicate a train of input pulses but which output pulses are delayed a selective amount in time. A first counter receives a digital word which represents the amount of time that the output is to be delayed after the input. A clock supplies the counter with timed pulses, and when the capacity of the counter has been reached, its output initiates the output pulse. A second counter counts upwardly during the period of time that an input pulse exists. Upon decay of the input pulse, the second counter is inhibited from further counting until the output from the first counter is generated. At that time, the second counter begins counting down, and when it reaches zero, an output signal is generated which terminates the output pulse.
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