PARTITIONING OF TASKS FOR EXECUTION BY A VLIW HARDWARE ACCELERATION SYSTEM
摘要
<p>In one aspect, logic simulation of a design of a semiconductor chip is performed on a domain-by-domain basis (e.g., by clock domain), but storing a history of the state space of the domain during simulation. In this way, additional information beyond just the end result can be reviewed in order to debug or otherwise analyze the design.</p>
申请公布号
WO2007067399(A2)
申请公布日期
2007.06.14
申请号
WO2006US45712
申请日期
2006.11.29
申请人
LIGA SYSTEMS, INC.;VERHEYEN, HENRY, T.;WATT, WILLIAM