| 摘要 |
A damping coefficient variation mechanism for a PLL including a bias controller, a gain control circuit, and an oscillator circuit. The PLL receives an input clock signal and provides an output clock at a frequency that is the frequency of the input clock multiplied by a clock multiplier. The bias controller has an input receiving a loop control signal and an output providing one or more bias signals. The gain control circuit has bias inputs receiving the bias signals, a gain control input receiving a gain control value, and an output providing a control signal. The oscillator circuit has an input receiving the control signal and an output providing the output clock signal. The gain control circuit provides the control signal to adjust frequency of the output clock signal based on the loop control signal at a gain determined by the gain control value.
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