ADDRESS DECODE LOGIC FOR A SEMICONDUCTOR MEMORY

摘要

One address line of a related pair of address lines implementing address decode logic for a semiconductor memory provides an electrical ground discharge path for itself and the adjacent address line of the related pair when neither line is addressed. When one line of the related pair of address lines is addressed, the unaddressed line is converted to an electrical ground line and the addressed line remains charged. The related pairs of address lines provide decode logic for addresses differing at only one bit position (X, X). The different bit positions are implemented by field effect transistors used in precharging the address lines and in evaluating the address input signals.