SEMICONDUCTOR MEMORY SYSTEM

摘要

A semiconductor memory system is provided to transceive data between a memory controller and a memory device by using a half-duplex mode SERDES(SERializer/DESerializer) chip, and reduce skew between pins and a manufacturing cost by reducing the number of pins, as a half-duplex mode is applied. The memory device(300) transceives a signal with the memory controller(100). The SERDES chip(200) selectively provides a path between the memory controller and the memory device to perform transmission/reception through one I/O(Input/Output) pin. The SERDES chip includes an instruction interpreter(260) selectively providing a controller and memory transmitter enable signal by receiving an instruction from the memory controller, a read replica circuit(280), and a write replica circuit(270). The read replica circuit synchronizes a time point for transmitting the data to the memory controller by responding to the controller transmitter enable signal. The write replica circuit synchronizes the time point for transmitting the data to the memory device by responding to the memory transmitter enable signal.