| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To enable adjustment about amount of delay by a constitution needless of a PLL circuit and an additional terminal, and needless of feedback means at an IC in its poster stage by measuring the amount of delay of a variable delay circuit. <P>SOLUTION: Only a signal for two cycles is to be extracted from an inputted clock signal by a gate signal producing circuit 30 and an AND gate circuit 20. Delay gate circuits 21 to 23 are each designed to output a clock signal for a cycle after being made to be sequentially delayed. Each of AND gate circuits 24 to 27 is designed to make each signal from delay gate circuits 21 to 23 pass through only when each of corresponding open/close control signals EN0 to 3 becomes "1" which is a high level. An OR gate circuit 28 is designed to calculate logical addition about output signals from the AND gate circuits 24 to 27, and to output to a T-FF circuit 29. The T-FF circuit 29 is designed to function as determining means for determining whether a slit width which is a width of a low level between two clock pulses to be outputted from the OR gate circuit 28 is existing or not. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
