| 摘要 |
PROBLEM TO BE SOLVED: To provide the design method of a semiconductor integrated circuit for improving the convergency of timing even in a circuit whose power consumption can not be logically reduced. SOLUTION: As for arrangement processing, initial arrangement S5-1 in consideration of only timing convergency and wiring congestion degree is executed. Then, voltage drop analysis S5-2 is executed, and the voltage drop quantity information of a whole chip and the voltage drop quantity information of each logical cell is acquired. Then, STA(static timing analysis) S5-3 in consideration of the voltage drop quantity is executed, so that timing information can be acquired, and a critical path is recognized according to the timing information. Detail arrangement processing S5-4 is executed by preferentially arranging the critical path at a position where the voltage drop quantity is small based on the arrangement information of the logical cells acquired by the step S5-1, the voltage drop quantity information of the whole chip and the voltage drop information of each logical cell acquired by the step S5-2 and the critical path information acquired by the step S5-3. COPYRIGHT: (C)2007,JPO&INPIT
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