发明名称 |
Type II phase locked loop using dual path and dual varactors to reduce loop filter components |
摘要 |
A phase locked loop (PLL) with reduced loop filter components having dual charge pumps and corresponding dual signal paths that reduce on-chip component size within the filters. The dual paths are combined advantageously via dual varactors within a voltage controlled oscillator to further reduce loop filter components. The PLL removes the drawbacks of noise introduced by circuitry normally used for summing dual path configurations.
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申请公布号 |
US2007126512(A1) |
申请公布日期 |
2007.06.07 |
申请号 |
US20050293162 |
申请日期 |
2005.12.05 |
申请人 |
SIRIFIC WIRELESS CORPORATION |
发明人 |
BELLAOUAR ABDELLATIF;FRIDI AHMED R.;BALASUBRAMANIYAN ARUL M. |
分类号 |
H03L7/00 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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