Memory circuit arrangement for use as e.g. floating gate memory, has memory reading/verification control circuit arranged to read and/or verify condition of each memory cells of memory cell array

摘要

The arrangement has a memory cell array including a set of nitrided read only memory (NROM) memory cells (102) that are arranged in rows and columns. A memory reading/verification control circuit controls a reading operation and/or verification operation on the memory cells of the array. The control circuit is arranged to read and/or verify a condition of each memory cells of the array according to reading and/or verification directive information on a memory cell level. A determination unit determines the memory cells for implementing reading and/or verification operations. An independent claim is also included for a method for reading and/or verifying a condition of memory cells of a memory cell array.