| 摘要 |
PURPOSE:To check various timing signals for memory control, by using a check clock generated with a prescribed phase as the check signal for memory timing signal. CONSTITUTION:A timing control circuit 2 giving various control timing signals to memory chip groups 1-1, 1-2 being memory element arrays is provided with an odd number of driver circuits which distribute control timing signals RAS, CAS, WE to the memory chips 1-1, 1-2 at every control timing signal. A logical circuit 6 forming exclusive logical sum signal for all the outputs of this driver circuit is provided, and the output signal of this logical circuit 6 and check clocks CHCL0, CHCL1 produced at a prescribed phase are inputted to NAND circuits 6, 7, the logical product is taken and the error check for the control timing signal is made. |
