发明名称 APPARATUS AND METHOD FOR DIGITAL LOGIC BLOCK REUSE
摘要 A device and a method for reusing a digital logic block are provided to reuse the digital logic block having a host bus interface and transceive correct data with the reused digital block by using two FIFO devices. The first FIFO device(412) temporarily stores an access signal for an address, data, and control signal for accessing the reused block(100). The second FIFO device(414) receives/temporarily stores output data output from the reused block or an acknowledge signal indicating that the reused block receives the access signal. A FIFO controller(416) stores the access signal to the first FIFO device if the access signal of the reused block is received, provides the access signal stored in the first FIFO device to the reused block according to a clock of the reused block, generates the acknowledge signal indicating that the access signal is completely processed, and stores the acknowledge signal to the second FIFO device.
申请公布号 KR20070056286(A) 申请公布日期 2007.06.04
申请号 KR20050114755 申请日期 2005.11.29
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 CHOE, CHAE KYU;KIM, AUSTIN
分类号 G06F13/00;G06F13/40;G06F15/163 主分类号 G06F13/00
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