| 摘要 |
An object of the present invention is to realize an at-speed test on a latch-to-latch path (a cross domain path) between different clock domains. In order to achieve the object, the present invention provides an integrated circuit which includes: a first flip-flop which is capable of flushing and which operates by using a first clock signal CLK 1 ; a second flip-flop DFF 2 which operates by using a second clock signal CLK 2 , and which is connected to the first flip flop; and a third flip-flop DFF 3 which operates by using the second clock signal CLK 2 , and which is connected to the first flip-flop. A test on a path between the first and second flip-flops is carried out in a manner that test data is released and captured on receipt of the clock signal CLK 2 between the second flip-flop DFF 2 and the third flip-flop DFF 3 via the first flip-flop DFF 1 , and that the test data is flushed by the first flip-flop DFF 1.
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