PHASE- OR FREQUENCY-LOCKED LOOP CIRCUIT HAVING A GLITCH DETECTOR FOR DETECTING TRIGGERING-EDGE-TYPE GLITCHES IN A NOISY SIGNAL

摘要

A phase- or frequency-locked loop circuit (200) that generates an accurate output signal (ACC_SYN_OUT) even in the presence of edge-triggering-type glitches ( 148, 304 A, 304 B) in the input reference clock signal (REF_CLK). The locked-loop circuit includes a phase or frequency difference detector ( 216 ) and a glitch detector ( 208 ) that generates a trigger signal (GLITCH_DETECTED) upon detection of at least one glitch. The trigger signal resets the difference detector so as to abort the updating of the output signal that the glitch would otherwise cause.