发明名称 DMA CONTROLLER AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To avoid loss of a reception packet for real-time communication even if the capacity needed for a packet communication function for providing real-time service decreases. <P>SOLUTION: A DMA controller 30 of the present invention performs transfer processing wherein storage of a reception packet in one of receiving FIFO memories 11 and 12 as a first-in first-out type transfer source storage means is detected and data are out of the reception packet and written to one of an RT buffer 50 and an NRT buffer 51 as a transfer destination storage means, and is equipped with a loss time measuring unit 33 which measures a loss time of the transfer processing, a transfer time monitor unit 35 which makes a request to cancel the transfer processing when the loss time exceeds a threshold, and a transfer cancellation unit 32 which reads and discards the data of the reception packet in the receiving FIFO memory when the transfer processing to another transfer destination storage means for the reception packet is completed or canceled, upon the request to cancel the transfer processing. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2007134936(A) 申请公布日期 2007.05.31
申请号 JP20050325741 申请日期 2005.11.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 IKOMA TATSURO
分类号 H04L12/70;G06F13/28;H04L12/823;H04L12/841;H04L12/853;H04L12/931 主分类号 H04L12/70
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