| 摘要 |
According to one embodiment, a synchronicity detecting circuit to which a wobble signal reproduced from a recording track is input and which detects a synchronizing signal in the wobble signal, a synchronicity detection flag generating section which generates a synchronicity detection flag of a first level when the synchronicity detecting circuit detects the synchronizing signal, and a counter and logic determining section which resets the synchronicity detection flag to a second level when the output synchronicity detection flag of the first level remains active and when the number of non-detections of the synchronizing signal meets a predetermined condition. A physical address is thus detected when the synchronicity detection flag is at the first level.
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