发明名称 Fast method for functional mapping to incomplete LUT pairs
摘要 A configuration for a programmable device is determined to implement an incomplete function using at least two logic cells. Function inputs are partitioned into portions associated with first and second logic cells. The partitioning is screened to determine if it is potentially acceptable by determining if a portion of the function can be implemented using a complete look-up table. If the partitioning of the function inputs is potentially acceptable, the function inputs are assigned to the input ports of the logic cells. Variables are assigned to look-up table locations and a correspondence is determined between function input and output values, the variables, and the look-up table locations. Boolean tautology rules are applied to the correspondence to simplify the variables. If the simplified variables are consistent, a configuration is output that includes assignments of function inputs to input ports and look-up table data based on the simplified variables.
申请公布号 US7224183(B2) 申请公布日期 2007.05.29
申请号 US20050201565 申请日期 2005.08.10
申请人 ALTERA CORPORATION 发明人 BAECKLER GREGG WILLIAM;VAN ANTWERPEN BABETTE
分类号 H03K19/173 主分类号 H03K19/173
代理机构 代理人
主权项
地址