| 摘要 |
FIELD: automatics and computer engineering, possible use for building corresponding end devices. ^ SUBSTANCE: in accordance to method, for generating sign of equality of two binary signals x1=x2∈{0,1}, setting compared one-bit numbers, these signals are added by modulus two adder, and addition results are inverted by NOT element, for creating a sign of relation x1 < x2, result of modulus two addition of given signals and binary signal x2 are sent to AND element. ^ EFFECT: simplified comparison of one-bit binary numbers due to ensured generation of signs of expressions x1=x2, x1<x2 by means of lesser number of logical elements. ^ 1 tbl |
