发明名称
摘要 A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate; dividing the base substrate into body regions and connection regions; thinning the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined cutting lines between the plurality of functional regions.
申请公布号 JP2007513507(A) 申请公布日期 2007.05.24
申请号 JP20060541821 申请日期 2004.11.15
申请人 发明人
分类号 H01L25/18;H01L21/50;H01L21/58;H01L23/48;H01L25/065;H01L25/07 主分类号 H01L25/18
代理机构 代理人
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