发明名称 |
Use of silicon block process step to camouflage a false transistor |
摘要 |
A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable. |
申请公布号 |
GB2422956(B) |
申请公布日期 |
2007.05.23 |
申请号 |
GB20060008053 |
申请日期 |
2003.11.20 |
申请人 |
HRL LABORATORIES LLC;RAYTHEON COMPANY |
发明人 |
LAP-WAI CHOW;WILLIAM M CLARK JR;GAVIN J HARBISON;JAMES P BAUKUS |
分类号 |
H01L27/02;H01L23/58 |
主分类号 |
H01L27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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