| 摘要 |
An electronic circuit includes a first and a second PLL stage (PLL 1 , PLL 2 ) that can be switched in parallel or in series depending on locking of the first one of the PLL circuits to an input signal (IN). When in parallel, only the second PLL circuit (PLL 2 ) is actively supplying a clock signal to the output of the electronic circuit. The first PLL circuit (PLL 1 ) continues trying to lock onto the input signal (IN). A lock detector (LD) monitors the locking status of the first PLL circuit (PLL 1 ) to the input signal (IN) and, upon locking, sets switches (S 1 , S 2 ) to couple the output of the first PLL circuit (PLL 1 ) to the input of the second PLL circuit (PLL 2 ), and to couple the output of the second PLL circuit (PLL 2 ) to the input of the first PLL circuit (PLL 1 ).
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