| 摘要 |
Twin side-by-side non-volatile memory transistors (17) have a common T-shaped control gate (57) over mirror image floating gates (53, 55) sharing a common subsurface electrode (52; 54; 56) between the floating gates. Select transistors (31, 33) on either side of the transistor pair, in combination with the common control gate (32; 34) allow selection of individual transistors in an array of rows and columns, without isolation between devices in the array. The device is made with three layers of polysilicon or poly. A first poly layer is used to form floating gates. A second poly layer is used for the T-shaped control gates. A third poly layer is used as a gate for select transistors between memory transistor pairs.
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