发明名称 |
DUTY CYCLE MEASURMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCED CLOCK DUTY CYCLE |
摘要 |
A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.
|
申请公布号 |
US2007103141(A1) |
申请公布日期 |
2007.05.10 |
申请号 |
US20070619475 |
申请日期 |
2007.01.03 |
申请人 |
|
发明人 |
DIXON ROBERT C.;FRANCH ROBERT L.;RESTLE PHILLIP J. |
分类号 |
G06M1/10;G01R31/317;G01R31/3185;G06F19/00 |
主分类号 |
G06M1/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|