发明名称 |
DUAL STRESS MEMORY TECHNIQUE METHOD AND RELATED STRUCTURE |
摘要 |
A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.
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申请公布号 |
US2007105299(A1) |
申请公布日期 |
2007.05.10 |
申请号 |
US20050164114 |
申请日期 |
2005.11.10 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
FANG SUNFEI;KIM JUN J.;LUO ZHIJIONG;NG HUNG Y.;ROVEDO NIVO;TEH YOUNG W. |
分类号 |
H01L21/8238 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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地址 |
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