发明名称 |
Power management circuit that qualifies powergood disposal signal |
摘要 |
A power recycle circuit is for use in a power management system. An input of the power recycle circuit is for receiving a clock signal. A detection circuit is for sensing a minimum disable pulse when a clock signal is received and when a clock signal is not received. A power recycle circuit is for generating a power recycle signal in response to the minimum disable pulse. A state machine is for holding the power recycle signal for at least two clock cycles.
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申请公布号 |
US6397338(B2) |
申请公布日期 |
2002.05.28 |
申请号 |
US19980105097 |
申请日期 |
1998.06.25 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
SHAY MICHAEL JOHN |
分类号 |
G06F1/04;G06F1/06;G06F1/08;G06F1/24;G06F1/32;H03L3/00;(IPC1-7):G06F1/26 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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