发明名称 NONVOLATILE SEMICONDUCTOR MEMORY
摘要 <p><P>PROBLEM TO BE SOLVED: To accurately perform determination of data in verify-read. <P>SOLUTION: A page buffer P/B has a latch circuit LATCH consisting of first and second inverters MP3, MP4, MN11, MN12 connected in a flip-flop type, a first transistor MN7 connected between a first node N1 of the latch circuit LATCH and a write-in circuit, and a second transistor MN5 which is connected between a second node N2 of the latch circuit LATCH and a ground point and in which data read out from a memory cell by verify-read is input to a gate. Input nodes of first inverters MP3, MN11 are connected to the first node N1, output nodes of the first inverters MP3, MN11 are connected to the second node N2, and a third transistor MP1 made into an off-state when data is input to the page buffer P/B is connected between the first inverters MP3, MN11 and a power source terminal Vdd. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2007115407(A) 申请公布日期 2007.05.10
申请号 JP20070024390 申请日期 2007.02.02
申请人 TOSHIBA CORP 发明人 IKEHASHI TAMIO;IMAMIYA KENICHI
分类号 G11C16/06 主分类号 G11C16/06
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