| 摘要 |
PROBLEM TO BE SOLVED: To output amplitude data with a clock frequency higher than that of phase data. SOLUTION: A direct digital synthesizer comprises a transmitting phase ACC (1) for outputting phase data (P1) with a clock frequency f1, a curtailing unit (5) for outputting phase data (P2) with a clock frequency f2 (<f1) by implementing curtailing process to the phase data (P1) and outputting additional data (A) for compensating for phase information disappeared by the curtailing, an interpolating unit (6) for outputting phase data (P3) with a clock frequency f3 (>f1) by implementing interpolating process to the phase data (P2), and a detecting waveform LUT (7) for outputting transmission amplitude data (S) based on the phase data (P3). According to the invention, the detecting signal amplitude data (S) can be outputted with the clock frequency f3 higher than the clock frequency f2 of the transmitted phase data (P2). COPYRIGHT: (C)2007,JPO&INPIT
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