发明名称
摘要 PROBLEM TO BE SOLVED: To enhance the operation efficiency of time adjustment of an electronic clock. SOLUTION: An analog electronic clock 10 has a receiving circuit 21 for receiving an adjustment mode release signal of an external adjustment device 30, and a mode control circuit 22. The mode control circuit 22 causes time measurement to take place, when the receiving circuit 21 receives the adjustment mode release signal of the external adjustment device 30.
申请公布号 JP3911970(B2) 申请公布日期 2007.05.09
申请号 JP20000199705 申请日期 2000.06.30
申请人 发明人
分类号 G04D7/00;G04C9/00;G04G21/04;G04R40/00;G04R60/02 主分类号 G04D7/00
代理机构 代理人
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