发明名称 |
Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices |
摘要 |
A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.
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申请公布号 |
US6969649(B2) |
申请公布日期 |
2005.11.29 |
申请号 |
US20040810884 |
申请日期 |
2004.03.29 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
SEKIGUCHI TOSHIHIRO;TADAKI YOSHITAKA;KAWAKITA KEIZO;AOKI HIDEO;KUMAI TOSHIKAZU;SAITO KAZUHIKO;NISHIMURA MICHIO;TANAKA MICHIO;YUHARA KATSUO;NISHIO SHINYA;KAERIYAMA TOSHIYUKI;CHO SONGSU |
分类号 |
H01L21/8242;H01L21/60;H01L27/108;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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