发明名称 |
Control signal generation for a low jitter switched-capacitor frequency synthesizer |
摘要 |
A phase detector and control signal generator responds to a reference signal and a feedback signal to produce a non-delayed up and down signal. A programmable delay unit delays the non-delayed up and down signal to provide up and down signals for a charge pump. A divider configured to respond to the up and down signals provides a divided clock signal. A non-overlapped clock generator configured to respond to the divided clock signal to provide non-overlapped hold even and hold odd signals for the switched-capacitor ripple-smoothing filter.
|
申请公布号 |
US7212051(B1) |
申请公布日期 |
2007.05.01 |
申请号 |
US20050260097 |
申请日期 |
2005.10.26 |
申请人 |
LATTICE SEMICONDUCTOR CORPORATION |
发明人 |
ZHU XIANG;QU MING;YUAN ZHENGYU |
分类号 |
H03L7/06;G01R25/00;H03L7/00;H03L7/089;H03L7/093 |
主分类号 |
H03L7/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|