发明名称 |
SUBLITHOGRAPHIC NANOSCALE MEMORY ARCHITECTURE |
摘要 |
<p>A circuit for selecting a nanoscale wire among a plurality of nanoscale wires is disclosed. The circuit comprises microscale ohmic contacts (110, 111, 112) arranged to be connected to a different subset of the plurality of nanoscale wires for selecting a specific subset of the plurality of nanoscale wires, and addressing wires (A0, A1, A13) arranged to be associated with the different subsets of the plurality of nanoscale wires, for selecting a nanoscale wire among the specific subset of nanoscale wires once the specific subset has been selected.</p> |
申请公布号 |
EP1525586(B1) |
申请公布日期 |
2007.04.25 |
申请号 |
EP20030796282 |
申请日期 |
2003.07.24 |
申请人 |
CALIFORNIA INSTITUTE OF TECHNOLOGY;PRESIDENT AND FELLOWS OF HARVARD COLLEGE;SRI INTERNATIONAL;BROWN UNIVERSITY |
发明人 |
DEHON, ANDRE;LIEBER, CHARLES, M.;LINCOLN, PATRICK, D.;SAVAGE, JOHN |
分类号 |
G11C13/00;G11C13/02;G11C8/10;H01L21/3205;H01L23/52;H01L23/522;H01L27/10;H01L29/06;H01L49/00 |
主分类号 |
G11C13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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