发明名称 Multiple critical paths having different threshold voltages in a single processor core
摘要 A processor having a multi-Vt critical path is provided that includes both low-Vt devices and high-Vt devices. If the processor is operating in a high performance mode, the multi-Vt critical path is controlled so as to use the low-Vt devices. Conversely, if the processor is operating in a low power mode, the multi-Vt critical path is controlled so as to use the high-Vt devices. In this fashion, the complication of multiple processing cores is avoided in that a single processor core can operate in both the high performance mode and in the low power mode.
申请公布号 US9348402(B2) 申请公布日期 2016.05.24
申请号 US201313771075 申请日期 2013.02.19
申请人 QUALCOMM Incorporated 发明人 Zanotelli Joseph Victor;Saint-Laurent Martin
分类号 G11C16/04;G06F1/32 主分类号 G11C16/04
代理机构 Haynes and Boone, LLP 代理人 Haynes and Boone, LLP
主权项 1. A multi-mode critical path for a central processing unit (CPU), comprising: an initial storage cell; a final storage cell, wherein both the initial storage cell and the final storage cell are configured to be clocked by a high speed clock during a high performance mode for the CPU and to be clocked by a low speed clock during a low performance mode for the CPU, and wherein a frequency for the high speed clock is greater than a frequency for the low speed clock; a plurality of first logic gates configured to form a first signal path between the initial storage cell and the final storage cell, wherein the plurality of first logic gates are configured to be operational during the high performance mode and to be non-operational during the low power mode, the plurality of first logic gates comprising devices configured to have at least one of a first channel length and a first threshold voltage; and a plurality of second logic gates configured to form a second signal path between the initial storage cell and the final storage cell, wherein the plurality of second logic gates are configured to receive power during the low power mode and to not receive power during the high performance mode, the plurality of second logic gates comprising devices configured to have at least one of a second channel length and a second threshold voltage, wherein the second channel length is longer than the first channel length and the first threshold voltage is lower than the second threshold voltage.
地址 San Diego CA US