| 摘要 |
The present invention is related to semiconductor memories, and in particular to a nonvolatile or flash memory and method that reduces the effect of any over- erased memory cells in a memory array (301) . When a memory cell (Ml 231, M2 232) is read, a read voltage (306) is applied to the control gate (CG<SUB>N</SUB>) of at least one target memory cell, and a negative bias voltage (308) that is lower than a threshold voltage of an over-erased memory cell is also applied to the control gate (CG<SUB>N-2</SUB>, CG<SUB>N+2</SUB>, ...) of at least one other memory cell that is in the same row as the target memory cell . Applying a negative bias voltage to these other memory cells shuts off nearby cells to isolate current that may come from over-erased memory cells during a read, program, or erase operation.
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