发明名称 Voltage regulator with common s-phase signals and phase lock loops
摘要 A voltage regulator coupled to an unregulated DC input voltage source by an input terminal, and to a load by an output terminal is disclosed. The voltage regulator converts an input voltage at the input terminal to an output voltage at the output terminal. The voltage regulator includes a master controller and one or more slaves, and each slave includes a switching circuit which serves as a power switch for alternately coupling and decoupling the input terminal to an intermediate terminal, and an internal controller which sends a same control signal to each slave. Each internal controller includes a phase-locked loop which offsets the control signal so that each slave is phase-offset relative to the other slaves.
申请公布号 US2007076455(A1) 申请公布日期 2007.04.05
申请号 US20060541503 申请日期 2006.09.28
申请人 BURSTEIN ANDY 发明人 BURSTEIN ANDY
分类号 H02J1/10 主分类号 H02J1/10
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