发明名称 |
Buffer device and method of operation in a buffer device |
摘要 |
An integrated circuit buffer device comprising a receiver circuit to receive control information and address information. A first interface portion provides at least a first control signal that specifies a write operation to a first memory device. The first control signal corresponds to the control information. A second interface portion provides a first address to the first memory device. The first address corresponds to the address information. The first address specifies a memory location for the write operation to the first memory device. A third interface portion provides a first signal to the first memory device. The first signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A fourth interface portion provides at least a second control signal that specifies a write operation to a second memory device. The second control signal corresponds to the control information. A fifth interface portion provides a second address to the second memory device. The second address corresponds to the address information. The second address specifies a memory location for the write operation to the second memory device. A sixth interface portion provides a second signal to the second memory device. The second signal synchronizes communication of the second control signal from the integrated circuit buffer device to the second memory device.
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申请公布号 |
US7200710(B2) |
申请公布日期 |
2007.04.03 |
申请号 |
US20050130734 |
申请日期 |
2005.05.17 |
申请人 |
RAMBUS INC. |
发明人 |
PEREGO RICHARD E.;SIDIROPOULOS STEFANOS;TSERN ELY |
分类号 |
G06F12/00;G06F13/16;G11C5/00;G11C7/10;G11C29/02 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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