| 摘要 |
PROBLEM TO BE SOLVED: To shorten a cycle time in a data read-out operation even in a ferroelectric memory on which an ECC (Error Checking and Correcting) circuit is mounted. SOLUTION: For example, potentials of plate lines PL0, DPL are made VAA, data of an unit cell UC is read out to a bit line BL0 and data of a reference cell RC is read out to a bit line /BL0. After that, potentials of the bit lines BL0, /BL0 are compared and amplified by a sense amplifier circuit 12. Also, after the potential of the bit line BL0 is transferred to an ECC circuit 16, a pass gate circuit 15 is cut off. After that, in a state in which potentials of plate lines PL0, DPL are made "L" , the potential of the bit line BL0 is set to VSS by a "0" write-in circuit 14. And after error correction processing by the ECC circuit 16, only when it is required that "1" data is written, rewriting of "1" data is performed for the unit cell UC. COPYRIGHT: (C)2007,JPO&INPIT
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