| 摘要 |
PROBLEM TO BE SOLVED: To provide an output buffer circuit capable of reducing output delay. SOLUTION: If a constant current source Is1 cannot follow and it does not change yet immediately after a signal Pen changes from L level to H level and a signal Nen changes from H level to L level, a node OUT remains at L level since a node P is still at H level. In this status, a node A connected to a node N of H level before change is connected to the node P of H level through the change. The node A changes from H level to L level via a capacitor C2 simultaneously with the connection, since an output unit of an inverter inv3 changes from H level to L level. Potential of the node P is reduced at this time until it becomes equal to the one of the node A, and the node P changes to L level. COPYRIGHT: (C)2007,JPO&INPIT
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